1. Field of the Invention
The present invention relates to static random access memories and more particularly, to static random access memories having a reduced soft error rate.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of structure of a static random access memory (referred to as a static RAM hereinafter).
In FIG. 1, a plurality of word lines and a plurality of bit line pairs are arranged intersecting with each other in a memory cell array 50, memory cells being provided at intersections of the word lines and the bit line pairs, respectively. The word lines in the memory cell array 50 are connected to an X decoder 51. X address signals are applied to the X decoder 51 through an X address buffer 52. In addition, the bit line pairs in the memory cell array 50 are connected to a Y decoder 54 through a transfer gate 53. Y address signals are applied to the Y decoder 54 through a Y address buffer 55.
One of the word lines in the memory cell array 50 is selected by the X address decoder 51 in response to the X address signals and one set of the bit line pairs in the memory cell array 50 is selected by the Y address decoder 54 in response to the Y address signals, so that a memory cell provided at an intersection of the selected word line and the selected bit line pair is selected. Data is written into the selected memory cell or data stored in the memory cell is read out. Writing or reading of data is selected by a read/write control signal R/W applied to a read/write control circuit 56. At the time of writing data, input data D.sub.in is inputted to the selected memory cell through a data input buffer 57. In addition, at the time of reading out data, data stored in the selected memory cell is extracted to the exterior through a sense amplifier 58 and a data output buffer 59.
FIG. 2 is a circuit diagram of a memory cell portion in a conventional static RAM which is disclosed in, for example, Japanese Patent Publication No. 18997/1987.
In FIG. 2, a plurality of memory cells 1a to 1n are connected between bit lines 14 and 15. Each of the memory cells 1a to 1n comprises two inverter constituting MOS field effect transistors (referred to as MOSFETs hereinafter) 2 and 3 of enhancement type, two load resistances 4 and 5 each having a high resistance value and two accessing MOSFETs 6 and 7. The MOSFETs 2 and 3 have respective their drains D connected to respective one ends of the resistances 4 and 5 at nodes 8 and 9, respectively, the respective other ends of the resistances 4 and 5 being connected to power supply terminals 10 and 11, respectively. In addition, each of the MOSFETs 2 and 3 has its source S connected to a ground terminal. Furthermore, the MOSFET 2 has its gate G connected to the node 9 and the MOSFET 3 has its gate G connected to the node 8. Information is stored in a parasitic capacitance 12 which exists between the node 8 and the ground terminal and a parasitic capacitance 13 which exists between the node 9 and the ground terminal. The node 8 is connected to the bit line 14 through the accessing MOSFET 6. The MOSFET 6 has its gate connected to a corresponding one of word lines 16a to 16n. The node 9 is connected to the bit line 15 through the accessing MOSFET 7. The MOSFET 7 has its gate connected to a corresponding one of the word lines 16a to 16n.
The bit lines 14 and 15 are connected to I/O lines 19 and 20 through MOSFETs 17 and 18, respectively. Each of the MOSFETs 17 and 18 has its gate connected to an input terminal 21 receiving a column selecting signal by a Y decoder. In addition, the bit lines 14 and 15 are connected to power supply terminals 24 and 25 through bit line load constituting MOSFETs 22 and 23 which have a diode-connection, respectively. The MOSFETs 22 and 23 precharge the bit lines 14 and 15, respectively. A power-supply voltage V.sub.CC is applied to the power supply terminals 10, 11, 24 and 25.
A threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set to be higher than a threshold voltage V.sub.TH of the other MOSFETs in the memory circuit. In addition, assuming that an on-resistance at the operating time of the MOSFETs 2 and 3 is represented by R.sub.DON, an on-resistance at the operating time of the MOSFETs 6 and 7 is represented by R.sub.TON and an on-resistance at the operating time of the MOSFETs 22 and 23 is represented by R.sub.LON, the threshold voltage V.sub.THD of the inverter constituting MOSFETs 2 and 3 is set as follows: ##EQU1## Where V.sub.RL represents a potential of the node 8 or 9 which stores data at a low level at the time of selecting the word lines.
Operation of the memory cell is now described.
It is assumed that data stored in the memory cell 1a is read out with the potential of the node 8 in the memory cell 1a being at a low level and the potential of the node 9 therein being at a high level. In this case, a potential on the word line 16a changes from 0V or a potential close to 0V at the time of non-selecting a word line to the power-supply potential V.sub.CC or a potential close to V.sub.CC at the time of selecting a word line. As a result, a current flows from the power supply terminal 24 to the ground terminal through the bit line load constituting MOSFET 22, the accessing MOSFET 6 and the inverter constituting MOSFET 2. However, since the inverter constituting MOSFET 3 is turned off, no current flows from the power supply terminal 25 to the ground terminal through the bit line load constituting MOSFET 23, the accessing MOSFET 7 and the inverter constituting MOSFET 3. Thus, a potential on the bit line 14 is set to a potential determined by the ratio of the on-resistances of the MOSFET 22, the MOSFET 6 and the MOSFET 2, while a potential on the bit line 15 is set to a potential which is lower, by the threshold voltage V.sub.TH of the bit line load constituting MOSFET 23, than the power-supply potential V.sub.CC.
In the above described conventional static RAM, since at the time of reading out data, the potential on the word line 16a is the power-supply potential V.sub.CC and the potential on the bit line 15 is lower, by the threshold voltage V.sub.TH of the MOSFET 23, than the power-supply potential V.sub.CC, a voltage between a gate and a source (which is connected to a bit line) of the accessing MOSFET 7 almost equals the absolute value of the threshold voltage V.sub.TH of the accessing MOSFET 7. Therefore, a sub-threshold current I.sub.subA flows in the accessing MOSFET 7, so that charges flow to the bit line 15 from the node 9 having the power-supply potential V.sub.CC stored therein. Thus, in the conventional static RAM, the potential at the time of storing data of a high level is lowered, so that soft errors are liable to occur.
Description is now made on soft errors in the RAM. Soft errors mean that information stored in a memory cell is lost by disturbance such as noise so that information "1" is inverted into information "0" or information "0" is inverted into information "1". Namely, soft errors mean that information is only inverted. More specifically, soft errors do not mean that structure of the memory cell is destroyed physically but that the state of a flip-flop in the memory cell only changes. Thus, when correct information is written to the memory cell, the correct information is stored therein. On the other hand, hard errors mean that a memory cell is destroyed physically so that information can not be stored therein any longer.
The problem to be considered in the present invention is soft errors generated by alpha particles, of soft errors. FIG. 3 is a cross sectional view showing a single storage node of the memory cell. In FIG. 3, upon incidence of alpha particles on an n.sup.+ layer 101 serving as a storage node of the memory cell or the vicinity thereof from exterior, electron and hole pairs are generated in a semiconductor substrate (P-well 102 herein) by energy thereof. Electrons, of the electron and hole pairs are attracted to the n.sup.+ layer 101 serving as a storage node. As a result, a potential of the storage node is lowered. When information at a high level is stored in the storage node, the information stored therein is inverted if the potential thereof is too lowered. Consequently, soft errors occur. Thus, when a potential of a node which stores information at a high level is lowered to some degree, soft errors are liable to occur.
Various research papers concerning soft errors in a static RAM have been presented. For example, an article in Japanese Journal of Applied Physics, Vol. 22, Supplement 22-1, 1983, pp. 69-73 shows that a soft error rate of an SRAM depends on a selected time interval of a memory cell. An article in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, June 1987, pp. 430-436 shows that since a memory cell in an SRAM requires several 10 .mu.s until a potential of a node of a high level is recovered after data is read out from the memory cell, a soft error rate is increased if the memory cell is operated in a cycle of several 10 .mu.s or less.